1. Field of the Invention
The present invention relates to an analog switch circuit and, more particularly, to an analog switch circuit composed of a CMOS structure and being free from malfunction by external noise signal.
2. Related Art
A typical conventional analog switch circuit that is formed on a monolithic integrated circuit to be used in a multiplexer or the like employs a CMOS structure with a view to widening the input voltage range of analog signals.
FIG. 1 shows one example in which a conventional analog switch circuit is applied to a multiplexer.
This circuit has analog switch circuits 10.sub.A to 10.sub.M each comprising a pair of P- and N-type transistors Q.sub.11 and Q.sub.12 which are parallel-connected between the corresponding one of the input terminals T.sub.A to T.sub.M and an output terminal T.sub.O and which are respectively supplied at their gate electrodes with the corresponding one of the control signals .phi..sub.A to .phi..sub.M from a decoder 2 and an inverted signal formed by respective inverters 3.sub.A to 3.sub.M so that the analog switch circuits 10.sub.A to 10.sub.M turn on/off.
FIG. 2 shows a sectional structure of respective analog switch circuits 10.sub.A to 10.sub.M. An N.sup.31 -type well region 12 is provided in a P.sup.- -type semiconductor substrate 11. A P-type transistor Q.sub.11 is formed in the well region 12 with P-type source and drain regions 13A and 14A and a gate electrode 16A, while an N-type transistor Q.sub.12 is provided directly in the semiconductor substrate 11 with N-type source and drain regions 13B and 14B and a gate electrode 16B. The semiconductor substrate 11 is grounded through a substrate grounding electrode through a substrate grounding region 17, while the well region 12 is connected to a power supply potential (V.sub.DD) terminal through the well-potential supplying region 15.
The above-described conventional analog switch circuits 10.sub.A to 10.sub.M are each comprised of a pair of P- and N-type transistors Q.sub.11 and Q.sub.12. The N-type transistor Q.sub.12 of each of the analog switch circuits 10.sub.A to 10.sub.M is formed directly in the P.sup.- -type semiconductor substrate 11 supplied with a grounding potential, while the P-type transistor Q.sub.11 is formed in a well region 12 provided in the semiconductor substrate 11 and supplied with a power supply potential V.sub.DD. Therefore, the conventional structure has the disadvantage that, if a noise or the like of a voltage which is out of the range defined by the power supply potential V.sub.DD and the ground potential is input to any of the input terminals T.sub.A to T.sub.M, a current flows between the one of input terminals T.sub.A to T.sub.M and the power supply potential V.sub.DD terminal through the P-type source region 13A-the well region 12-the well potential supplying region 15 or the ground potential terminal through the N-type source region 13B-the substrate 11-the substrate grounding region 17. This current flow changes the channel potential of the transistor Q.sub.11 or Q.sub.12 so that the noise or the like is transmitted to the output terminal T.sub.O, thus causing an adverse effect on the output signal OUT.
More specifically, it is assumed that a negative overvoltage is applied as a noise to the input terminal T.sub.A in the case where the control signal .phi..sub.A is at a high level and the transistors Q.sub.11 and Q.sub.12 of the analog switch circuit 10.sub.A are in an off-state and therefore the input terminal T.sub.A and the output terminal T.sub.O are not in electrical connection with each other, while another control signal .phi..sub.B is at a low level and the transistors Q'.sub.11 and Q'.sub.12 of the analog switch 10.sub.B are in an on-state and therefore the input terminal T.sub.B and the output terminal T.sub.O are in electrical connection with each other.
In such a case, if the negative overvoltage is applied to the source region 13.sub.A through the input terminal T.sub.A, since the gate electrode 16.sub.A is at a high level, the transistor Q.sub.11 is not turned on. However, if the negative overvoltage is applied to the source region 13.sub.B, a forward-biased diode is formed between the P.sup.- -type semiconductor substrate 11 and the N.sup.+ -type source region 13.sub.B, so that the applied negative overvoltage causes a current to flow between the ground potential terminal and the input terminal T.sub.A through the substrate grounding electrode 17. Further, the transistor Q.sub.12 which is turned off in the case where the gate electrode 16.sub.B is at a low level, that is, a level substantially equal to the ground potential, and the gate-to-source voltage V.sub.GS of the transistor Q.sub.12 is lower than the threshold voltage V.sub.TH is turned on since the source region 13.sub.B is at a negative potential and hence the gate-to-source voltage V.sub.GS is higher than the threshold voltage V.sub.TH despite the fact that the potential at the gate electrode 16B is substantially equal to the ground potential. As a result, the negative overvoltage signal applied to the input terminal T.sub.A is undesirably transmitted to the output terminal T.sub.O through the analog switch circuit 10.sub.A which has been set in an off state, thus causing an adverse effect on the output signal OUT.
When a positive overvoltage which is higher than the power supply voltage V.sub.DD is applied as a noise to the input terminal T.sub.A, the transistor Q.sub.11 is turned on in reverse to the above, thus similarly causing an adverse effect on the output signal T.sub.O.